1. Field of the Invention
The present invention relates to maintaining data coherency and consistency ("transaction ordering") in data transfer operations which occur asynchronously from their corresponding interrupt signals. More particularly, the present invention relates to reliable interrupt generation and reception over a buffered bus.
2. The Background
Asynchronous communication between computer system components, such as controlling the flow of data operations between peripheral devices ("peripherals"), and a host processor through a buffered bus using interrupt signals ("interrupts") to advise the host processor of a request for a particular operation, are known in the art.
Referring now to FIG. 1, peripherals such as network interface modules (port adapters) 10, 12 connect network media from networks 14, 16, respectively, to a first bus 18 which may be a PCI (peripheral component interchange) bus or a similar tppe of bus. Other peripherals such as a storage adapter 20, display adapter 22 and audio adapter 24, to name a few, may also be attached to first bus 18 as shown in FIG. 1.
A second bus 26, preferably using a first bus architecture such as a local bus architecture couples one or more host processors 28 with one or more instances of host memory 30.
A bridge 32 with buffering capability is used to couple a first bus 18 (there may be one or more instances of first bus 18 and bridge 32) to second bus 26.
When a peripheral has data requiring processing by host processor 28, two events occur asynchronously. In the first event, the peripheral performs a write transaction which includes sending the data to host memory 30 through first bus 18, buffering bridge 32 and second bus 26. The write transaction includes an address phase indicating a target location in host memory 30 and at least one data phase indicating the data to be stored in host memory 30, thus data is typically sent in a number of data blocks including data and header information indicating address information. In the second event, the peripheral uses an interrupt request to notify host processor 28, even when host processor is busy (such as when it is executing program code), that a data transaction needs to be processed. The interrupt reaches host processor 28 through first bus 18, bridge 32 and second bus 26. Host processor 28 then responds to the interrupt request by accessing the data from host memory 30 and sends an acknowledgement signal back to the originating peripheral over second bus 26, bridge 32 and first bus 18.
Using first bus 18 and bridge 32 to send data and interrupt requests to host processor 28 presents a number of disadvantages. First, a delay period ("latency") is incurred between the time that the interrupt request is sent to first bus 18 and the time that it is received by host processor 28. Second, this latency may be increased depending upon the number of peripherals arbitrating for the use of the first bus 18. Furthermore, such an approach inherently creates a race condition between data to be processed by host processor 28 and the interrupt requests corresponding to that data. Such a race condition can sometimes result in the interrupt being received and acted upon by host processor 28 before the corresponding data has been received in host memory 30. In such a situation, data may be lost.
Some solutions to the race condition problem exist. In accordance with one solution, the peripheral signaling the interrupt performs a read of the data written to host memory 30 to verify receipt in memory prior to sending the interrupt signal over the buffered bus to the host processor 28. This solution is easy to implement. Having the peripheral perform the read is much better than having the host processor perform the read from a processor throughput point of view. A major disadvantage is that the peripheral must execute a read cycle over the bus which could take a relatively long time due to bus arbitration and time required to traverse all bridges (there may be more than one) in the path. Another problem with this solution is that it can have the side effect of providing the host processor 28 with a spurious interrupt This can happen when (1) the peripheral device writes block 1 of data and block 2 of data into host memory 30; (2) the host memory 30 receives block 1 and block 2; (3) the peripheral device begins reading the host memory to verify receipt and reads block 1; (4) the peripheral device generates an interrupt for block 1 to the host processor 28; (5) the receipt of block 2 by the peripheral device is delayed due to latency; (6) the host processor 28 receives the first interrupt, acknowledges it and acts on it by processing all of the contents of host memory 30 including block 1 and block 2; (7) the read of block 2 by the peripheral device is completed and the peripheral device sends a second interrupt request to the host processor 28; and (8) the host processor 28 acknowledges and acts on the second interrupt only to find that it has already processed the contents of host memory 30.
In another solution the host processor 30, or a device associated with it, performs a read operation to a register of the peripheral device in response to receipt of the interrupt request before accessing the data written by the peripheral into host memory. This guarantees that all of the data to be written to the host memory will necessarily have cleared the buffers before this step can be completed. This approach can increase latency because the read operation can be further delayed due to bus arbitration issues under loaded conditions.
In accordance with yet another solution shown in FIG. 2, a separate non-buffered path (34, 35, 38, 40, 42) is provided for each peripheral to signal the interrupt request to a special interrupt input register 44 in the host processor. This approach requires the provision of a separate path outside the bus structure for each such peripheral used for data communication and therefore requires special purpose hardware. This approach is also subject to a race condition because the interrupt can arrive before all data has cleared all intermediate buffers.
Accordingly, a need exists for a method and apparatus for reliable generation, transmission and reception of interrupt requests over buffered buses without the interrupt requests incurring significant delay due to buffering and without creating a race condition between the interrupt requests and corresponding data.